TSMC to use ArF immersion lithography all the way down to 10 nm feature sizes

July 8, 2013
Hsinchu, Taiwan--In an interview, Burn J. Lin, vice president of research and development at TSMC (Taiwan Semiconductor Manufacturing Co. Ltd.) described the company's roadmap for its future computer-chip lithography production techniques as it tries to keep in line with Moore's Law.
Tech-On!
Burn J. Lin, vice president of research and development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) says a quadruple patterning process will allow the company to produce silicon chips with feature sizes down to 10 nm using conventional argon fluoride (ArF) lithography at a 193 nm wavelength.
Burn J. Lin, vice president of research and development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) says a quadruple patterning process will allow the company to produce silicon chips with feature sizes down to 10 nm using conventional argon fluoride (ArF) lithography at a 193 nm wavelength.

Hsinchu, Taiwan--In an interview, Burn J. Lin, vice president of research and development at TSMC (Taiwan Semiconductor Manufacturing Co. Ltd.) described the company's roadmap for its future computer-chip lithography production techniques as it tries to keep in line with Moore's Law. The interview was conducted by Nikkei BP Semiconductor Research.

Because the development of extreme ultraviolet (EUV) lithography is behind schedule throughout the industry, TSMC will continue to use its argon fluoride (ArF) immersion lithography (which relies on 193-nm-emitting ArF excimer lasers), which the company introduced for the 40 nm process, for 28, 20, 16, and 10 nm processes. While TSMC has been using single-patterning lithography based on ArF immersion for the 28 nm and older processes, it will introduce a double-patterning technology, which splits the pattern pitch formed in the first lithography in half, for the 20 nm process.

TSMC has already been using a method to form patterns using double exposures to trim the edges of patterned lines. But, as Lin says, "For the 20 nm process, we started to use it in the aim of splitting pitch in half for the first time." The company started trial production with the 20 nm process in 2013.

For the 16 nm process, with which TSMC will start trial production in 2014, the company will introduce a FinFET technology using a 3D channel structure. As a result, the power consumption and performance of the resulting chips will be improved.

However, TSMC basically will not change the design rules for metal wiring. So, the density (pitch) of circuit patterns with the 16 nm technology will be equivalent to that of the 20 nm technology. In other words, the company will not make major changes to the lithography technology. Still, Lin says, "We need to make improvements to the lithography technology to cope with the 3D structure of the FinFET."

For the 10 nm process, which will start trial production sometime between the second half of 2015 to the first half of 2016, the company will introduce a quadruple patterning technology, which will narrow pitch to 1/4 the projected pattern's pitch, for some critical layers while using ArF immersion.

Also, TSMC plans to use its EUV lithography technology for some layers in the 10 nm or 7 nm generation if technology development proceeds smoothly. The schedule for the trial production with the 7 nm process has not been determined yet. But it is expected to start in 2018according to Moore's Law.

Source: Tech-On! at: http://techon.nikkeibp.co.jp/english/NEWS_EN/20130702/290691/

About the Author

John Wallace | Senior Technical Editor (1998-2022)

John Wallace was with Laser Focus World for nearly 25 years, retiring in late June 2022. He obtained a bachelor's degree in mechanical engineering and physics at Rutgers University and a master's in optical engineering at the University of Rochester. Before becoming an editor, John worked as an engineer at RCA, Exxon, Eastman Kodak, and GCA Corporation.

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