Leuven, Belgium--By jumping from a 193 nm photolithographic exposure wavelength to the 13.5 nm wavelength planned for extreme-UV lithography (EUVL), computer-chip makers plan to stay on track with Moore's Law even after they run out of linewidth-reducing optical tricks at 193 nm. This switchover point will have to happen soon, which is why the lithography industry is working feverishly on EUVL technology.
What are the critical areas that need to be made production-worthy for EUVL to work? There's the light source (such as Cymer's laser-produced-plasma source), as well as the optical system (for example, ASML's all-mirror optics with a resolution of 10 nm and potentially smaller) and the photoresist. But since the 2009 International EUVL symposium held Oct. 18 to 23 in Prague, Czech Republic, the creation of a photomask (also called a reticle) of high-enough quality has become the number-one critical issue in preparing EUVL for high-volume manufacturing.
Combining three kinds of defect measurement
At IMEC, researchers are using a combination of three inspection techniques--blank inspection, patterned-mask inspection, and wafer inspection--to evaluate the "defectivity" level of state-of-the-art reticles for EUVL. IMEC uses the combined techniques, followed by wafer review, as the most suitable method to qualify defect densities of EUV masks.
A blank is the starting material for the fabrication of the mask. Mask defects can be due to the pattern or due to the blank. Wafer-inspection detection is confined to detecting repeating defects among multiple exposures, as these represent mask defects. The correlation of the defect maps obtained from each of the three types of inspections is crucial, because at present, none of the available inspection methods is sensitive enough on its own to find all defects.
By using this combined inspection, the defectivity level of state-of-the-art EUV reticles can be investigated. In addition, possible gaps in the available EUV mask-inspection infrastructure can be identified; these will need to be closed before EUV is ready for the production of integrated circuits.
So-called multilayer (ML) defects are considered especially critical and are specific to EUVL. The ML mirror is a so-called quarter-wave stack. A deformation just a few nanometers high in the upper part of the EUV mirror can be enough to cause a printing defect. Such a ML defect cannot be readily repaired, as it would require an extremely difficult local modification of the mirror for each and every defect. Work at IMEC has shown that it can be possible to compensate for the presence of a ML defect by absorber-pattern biasing; however, the limitation of this approach shows that ML defects must be avoided beforehand, while the reticle is still in the blank phase.
The record defect density of a present "champion" reticle is 0.53 defect/cm2. Only small fractions of those are considered to be ML-type. Yet, it is thought that inspection-tool limitations and line-edge roughness of the wafer pattern presently keep more defects from being revealed. Although this low defect density is very encouraging, it is still more than ten times higher than the industry's target of a defect density below 0.04 defect/cm2. Ideally zero defect density should be achieved, but this is considered extremely challenging. The defect density of 0.04 defect/cm2 assumes that such a level can be used for memory manufacturing, for which cell-redundancy is applied.
Now, with its most-critical challenges being arduously whittled down to a manageable level, it appears that the coming of EUVL is, at last, inevitable.
