IMEC and Riber collaborate on Ge and III-V semiconductor devices

May 17, 2006
May 17, 2006, Rueil-Malmaison, France and Leuven, Belgium--Riber, a supplier of MBE products and services to the compound semiconductor community, joins IMEC's Industrial Affiliation Program (IIAP) on Germanium (Ge) and III-V devices for CMOS beyond the 22nm node.

May 17, 2006, Rueil-Malmaison, France and Leuven, Belgium--Riber, a supplier of MBE products and services to the compound semiconductor community, joins IMEC's Industrial Affiliation Program (IIAP) on Germanium (Ge) and III-V devices for CMOS beyond the 22nm node.

The availability of a unique molecular beam epitaxy (MBE) cluster at IMEC, the Belgian nanoelectronics and nanotechnology research institute, will enable IMEC and its partners to create fundamental know-how on Ge and III-V processing and to develop the core technology ingredients.

The program aims to demonstrate that the introduction of Ge and III-V materials allows for CMOS scaling beyond 22nm. Moreover, this collaboration will form the base for a possible extension of the IIAP on Ge and III-V devices beyond mere CMOS into the area of photonic applications.

Research will be performed on Riber's ultra-high vacuum molecular beam epitaxy cluster system for 200mm. It includes a III-V compound semiconductor growth chamber and a metal/oxide deposition chamber which will be installed in IMEC's clean room.

The unique cluster will allow both deposition of compound semiconductor layers on GeOI or other Ge substrates and deposition of high-k dielectrics and metal gates on Ge and on III-V materials. This is considered as a potential enabling technology to make aggressively scaled devices in CMOS beyond 22nm.

The semiconductor industry has cited Ge as a potential replacement for planar silicon, since silicon is unlikely to accommodate the rigorous scaling requirements of sub-22nm geometries. The attractive properties of Ge, such as higher mobility resulting in lower intrinsic gate delay make it an excellent candidate for high-performance CMOS devices, allowing companies to leverage their existing silicon manufacturing infrastructure.

Last year, IMEC has already successfully demonstrated the feasibility of sub-micron pMOS devices on GeOI substrates. To solve the problems that occur with processing Ge nMOS transistors, III-V nMOS devices on the same Ge substrates are targeted. The process will be based on silicon wafers enabling manufacturing in a standard silicon process line using advanced CMOS compatible equipment.

One of the most demanding challenges is to improve the gate stack for MOS devices on Ge as well as on III-V compounds. The Riber MBE cluster will play a crucial role in this development.

The Ge and III-V devices program is part of IMEC's sub-45nm CMOS research platform which is being executed with IMEC's core partners Infineon, Intel, Matsushita/Panasonic, Philips, Samsung, ST Microelectronics, Texas Instruments and TSMC all world leading IDM and/or foundry companies.

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