Novel design cools arrays efficiently

Narrow bandwidth emission, high efficiency, and long-term reliability are just some of the features fueling the popularity of laser-diode arrays in applications such as laser pumping. The problem is that the small footprint combined with the high output power of a semiconductor laser can lead to heat fluxes as high as 1 kW/cm² at the junction. Because the junction must stay below 50°C for efficient operation, low-thermal-impedance packaging is a key design consideration. Thermal management will be even more critical in the future as bar power outputs increase.

Currently, the most efficient thermal management strategy revolves around microchannel cooling technology, in which the laser bar is individually bonded onto a multilayered heat sink and cooled by narrow channels beneath the diode. There is, however, a design disadvantage related to the large number of components, including water gaskets, and the moderate-to-low diode pitch, which is in the neighborhood of 1.0 to 1.7 mm. Now research at Lawrence Livermore National Laboratory (LLNL; Livermore, CA) indicates that it may be possible to work around this drawback using a heat-sink design that combines the high thermal performance of microchannels with the simplicity found in diode arrays that rely on a single common-backplane cooler.¹ (The common-backplane design, while easier to fabricate, has a nominal increase in thermal resistance of approximately five times compared to microchannels).

The microchannel-cooled heat sink developed at LLNL allows several bars to be bonded simultaneously to a monolithic substrate with negligible thermal crosstalk. The array's microchannels are produced in (110) silicon wafers 750 µm thick. Using double-sided alignment, the scientists simultaneously etch v grooves on the top side of the wafer and microchannels on the bottom. Anisotrophic wet etching then forms features that terminate when the (111) crystal planes are exposed. This termination allows the part geometry to be controlled within ±2 µm for all relevant dimensions independent of etch time.

The LLNL scientists designed the array so that each slot in the wafer feeds two adjacent sets of microchannels approximately 28 µm wide on a 60-µm pitch. Each v groove has a 1600-µm-wide opening to accept 1-mm-cavity-length diodes. The spacing between v grooves is 1.7 mm, but the pitch along the optical axis normal to the diode emission is 0.98 mm.

Etched wafers are diced into 10-bar units, anodically bonded to ultrasonically machined borosilicate glass blocks, and then metalized. The researchers use a dicing saw to slice a notch to one side of the vertex of the v groove to electrically break the metalization between diodes, and a thin film of indium is evaporated onto the sidewall where diodes will be located. Diode bars are inserted into the grooves with the back facets mounted flush against the opposing sidewall for accurate registration. Indium-coated copper ribbons are then bent in a v shape placed on top of them. All components are heated in an oven to melt the indium in a hydrogen atmosphere without the use of flux.

The LLNL team used commercially supplied diode bars with a nominal emission wavelength of 805 nm, a 90% fill factor, and a 1-mm cavity length.

The final 10-bar array has a continuous-wave (CW) thermal resistance of 0.032° C/W which the scientists say matches the performance of discrete microchannel-cooled arrays. The 1.46-kW maximum power level achieved at the supply limit of 165 A is reportedly the highest CW exitance from a stacked diode array with a monolithic heat-sink structure in this wavelength range.

REFERENCE

1. J. A. Skidmore et al., Appl. Phys. Lett. 77, 10 (July 3, 2000).