In August 2026, Lightmatter and 18 other companies published a white paper¹ through the Open Compute Project (OCP), specifying a standardized architecture for copackaged optics (CPO) for AI infrastructure. The Open Silicon Photonics for AI Systems initiative is an ambitious goal of a common multivendor reference architecture that lets AI clusters scale from 72 nodes to more than 1,024 while staying interoperable across switch vendors, XPU generations, and SerDes speeds.

During the past two years, the semiconductor industry was building CPO point solutions separately—each hyperscaler negotiated its own design, thermal budget, and optical input/output (I/O) density with whichever vendor would commit to a roadmap. Little of this work carries over from one deal to the next. Test infrastructure gets rebuilt, connector tooling is requalified, and thermal solutions are redesigned around a package that differs from the last one in ways that matter mechanically but not architecturally. A shared reference architecture cuts a large amount of this duplication and gives the broader supply chain a stable target to design against instead of a moving one.

But standardizing the rack-level architecture answers only part of the question the industry needs to be asking. It says nothing about whether the materials beneath this architecture can be produced at the volume, consistency, and speed the roadmap assumes. On the substrate side, wafer-level engineering will be crucial for the success of standardized CPO long before rack-level architecture.

Copper ran out of road

The OCP white paper clearly lays out the physics driving the transition to a centralized CPO design. As SerDes rates climb toward 448 Gbps per lane, copper’s usable reach shrinks to tens of centimeters, which is well short of what a multi-rack scale-up domain needs.

Earlier interconnect generations could absorb longer copper runs at the cost of some signal margin. At 448G, the reach simply isn’t there. And the usual compensations make the problem worse rather than better, with retimers and redrivers buying distance by spending power and adding latency, which is exactly the trade a scale-up fabric can least afford. Vendors building toward these speeds keep arriving at the same conclusion independently where optics have to move inside the package. It’s one of the reasons why a shared architecture is achievable now in a way it wasn’t three years ago. When everyone is solving the same physical problem, standardizing the solution becomes possible.

The coalition’s announcement is deliberately a technology-agnostic framing of multi-vendor interoperability. This is a necessity because no single photonic integration approach has fully won. It also means the substrate layer beneath each of these approaches must independently meet a much higher bar than the rack spec alone implies.

The substrate is not a commodity input

Photonics-silicon-on-insulator (Photonics-SOI) is the foundation for CPO. But we should be discussing how much tighter the manufacturing tolerances are than those of radio frequency-SOI (RF-SOI) and partially depleted-SOI (PD-SOI) substrates the industry has produced at scale for two decades.

A Photonics-SOI wafer carries a top silicon device layer, which is <220-nm thick and sits on a buried oxide layer ranging from 50 nm to several microns. Its top layer is where light propagates and functions as the waveguide core, so its thickness is an optical parameter. RF-SOI applications can tolerate thickness variation across a wafer of a few nanometers with no meaningful performance loss, but Photonics-SOI can’t. The uniformity requirement is roughly an order of magnitude tighter because small variations in silicon thickness change the waveguide’s effective index and shift the optical phase as light travels down it.

Push this phase drift far enough and modulator extinction ratios degrade, ring resonators fall out of resonance, and the yield of an entire optical engine collapses because the wafer underneath it isn’t uniform enough. Resonant devices are the least forgiving of all—a ring that drifts off resonance can often be pulled back with a thermal tuner, but every milliwatt spent heating a ring is a milliwatt subtracted from the power budget that justified copackaging in the first place. Most of these failures surface at optical testing after the wafer has accumulated its full packaging and assembly value.

A standardized module hardware system (MHS)-based CPO architecture can specify optical I/O density, connector pitch, and power envelopes with real precision. It has no mechanism to specify how a wafer supplier can maintain buried-oxide and top silicon layer uniformities across a 300-mm substrate at the volumes hyperscalers need. Layer transfer is a process where the learning is empirical and cumulative.

CPO changes wafer math

There’s a supply chain dimension that goes unappreciated in conversations focused on architecture and interoperability, and it’s worth precisely stating the mechanism because a loose version of this argument doesn’t hold up.

Moving an optical engine from a faceplate module into the package doesn’t, by itself, change how much photonic die area a given bandwidth requires. A 51.2T switch needs 51.2T of electro-optic conversion whether it happens in 64 pluggables or in eight copackaged engines. Anyone arguing that CPO multiplies photonic silicon consumption purely because the engines are distributed rather than concentrated has the math wrong, and the argument falls apart when you talk to someone who builds these systems.

The first is material substitution. A large share of today’s high-speed pluggables are built on indium phosphide (InP) with electro-absorption modulated lasers (EMLs), and this volume never touches a Photonics-SOI wafer. CPO designs are effectively all silicon photonics, so the transition converts a substantial block of transceiver demand from III-V substrates onto photonics-grade SOI. This shift is already underway independently of CPO, pushed along by well-documented InP and EML capacity constraints, but CPO makes it structural rather than opportunistic.

The second is optics intensity, because the number of optical lanes surrounding each accelerator is rising faster than compute die area. Each new platform packs more optics around roughly the same silicon.

The third is scope, because scale-up domains that were copper are becoming optical. It’s a category of photonic content that didn’t previously exist, and it scales with the size of the coherence domain rather than with the number of racks.

Substrate supply chain must scale faster

If it’s even directionally right, the OCP initiative’s success depends on the photonics-grade substrate supply chain scaling several times faster than the pluggable-optics supply chain it’s displacing—at a moment when the number of qualified suppliers of 300-mm photonics-grade SOI remains small. 

Foundries have built capable silicon photonics process platforms, such as GlobalFoundries’ Fotonix and Tower’s PH18, and each depends on photonics-grade SOI as its starting material. These platforms now sit downstream of a substrate-qualification bottleneck. Standardizing the rack architecture adds no capacity at this layer. It makes the demand on this layer more predictable and likely larger.

What should standardization mean for substrate suppliers?

When hyperscalers request different package sizes or power budgets, substrate suppliers end up certifying a dozen near-identical versions of the same wafer. Each variant needs its own lot history, reliability data, yield learning, and more. Manufacturing volume fragments across SKUs that individually never reach efficient scale, and the qualification effort scales with the number of specifications. A shared reference architecture, by contrast, lets substrate roadmaps consolidate around fewer specifications. This consolidation also shortens the lead time to add capacity, because equipment can be committed against a spec that will still exist three years later. This is the scenario in which the supply chain can realistically keep pace with OCP’s own targets for scaling clusters past 1,024 nodes.

It also changes what interoperability needs to mean at the material level. The white paper’s technology-neutral approach to silicon photonics, vertical-cavity surface-emitting lasers (VCSELs), and micro-light-emitting diodes (LEDs) is a reasonable architectural policy. But each approach places different demands on its substrate. VCSEL and silicon photonics designs need different wafers, even when they end at the same connector.

If multi-vendor interoperability at the rack level is the goal, then the standards conversation needs to go down an additional layer and define what qualified substrate performance means for each technology option the architecture is supposed to accommodate. This means agreed metrics and measurement methods for thickness uniformity, defectivity, and surface roughness, so a foundry can state a requirement once compared to having to negotiate it with every supplier. Right now, this work happens bilaterally between individual substrate suppliers and individual foundries. It would benefit from the same open, cross-industry coordination OCP has applied to rack architecture.

Energy efficiency traces back to the wafer

The energy efficiency gains that make CPO worth its engineering complexity depend on how little optical signal is lost as light moves through the waveguide. Insertion loss in a silicon photonic waveguide depends on sidewall roughness and thickness uniformity of the top silicon layer. A substrate with excellent uniformity lets designers run optical links at lower laser power for the same bit-error-rate target. A substrate with marginal uniformity forces compensation with higher laser drive current, more aggressive forward error correction, more conservative link margins, and more thermal tuning on resonant structures. Each of these negates the power savings that justified moving to CPO.

The system-level efficiency figures quoted are achievable because of decisions made at the wafer level long before any package is assembled. No amount of clever switch design or package engineering recovers optical performance lost to a substrate that wasn’t uniform enough to begin with.

Where does this leave the industry?

The OCP’s Open Silicon Photonics for AI Systems initiative is a meaningful step, and the breadth of its member list—spanning system integrators, ODMs, test equipment makers, and chip designers—suggests the industry understands CPO can’t be solved by any single company’s roadmap.

Architecture standardization and materials readiness are separate problems converging on the same timeline. The first is largely a coordination challenge, and coordination among 19 companies with competing commercial interests is difficult but tractable, as their white paper demonstrates. The second is a manufacturing physics challenge that coordination alone can’t solve. It yields to sustained investment in substrate engineering, much of it accumulated more than two decades before CPO became a commercial priority for anyone.

As the reference architecture moves from white paper to implementation, the manufacturers and hyperscalers driving demand behind it should treat substrate qualification and supply chain capacity as a first-class element of the standard and not an assumed input. It means publishing substrate requirements alongside the rack specification, agreeing on how to measure these requirements, and giving suppliers enough demand visibility to commit capital.

The rack architecture tells you how the optics should connect, but says nothing about whether the wafer underneath these optics can be built to the required tolerance at the volume the roadmap assumes by more than a small number of qualified suppliers. It’s the question the next phase of this initiative needs to answer, and one the semiconductor industry has been living with for considerably longer, before the commercialization of CPO. 

REFERENCE

1. www.opencompute.org/documents/vision-opensiphforaisystems-final-pdf.