IMEC demonstrates double patterning immersion litho for 32nm node

Oct. 19, 2006
October 19, 2006, Leuven, Belgium--IMEC in collaboration with ASML (Veldhoven, The Netherlands) has demonstrated the potential of double patterning 193 nm immersion lithography at 1.2 NA to create 32 nm node Flash memory and logic circuits. These results indicate that double patterning might offer an intermediate solution before extreme ultraviolet (EUV) lithography and very high NA (beyond water) 193 nm immersion lithography will be ready for production.

October 19, 2006, Leuven, Belgium--IMEC in collaboration with ASML (Veldhoven, The Netherlands) has demonstrated the potential of double patterning 193 nm immersion lithography at 1.2 NA create 32 nm feature sizes on Flash memory and logic circuits. These results indicate that double patterning might offer an intermediate solution before extreme ultraviolet (EUV) lithography and very high NA (beyond water) 193 nm immersion lithography will be ready for production. Meanwhile, installation of both ASML's XT:1700i immersion scanner and EUV alpha demo tool (ADT) continue at full speed in IMEC's clean room for 300 mm wafers.

The promising double patterning results were obtained by splitting gate levels of 32 nm half pitch Flash memory cells as well as logic cells into two complementary designs. The splitting was done automatically using software from electronic design automation (EDA) partners in IMEC's lithography program. After splitting, both designs received optical proximity corrections (OPC) and a classical lithography "litho-etch-litho-etch" sequence was performed. Exposures of both lithography steps were carried out on an XT:1700i immersion scanner at ASML.

These results indicate that the XT:1700i 193 nm immersion tool, which has a maximum NA of 1.2, can be extended beyond the 45 nm node for circuit feature sizes. Since both hyper NA 193 nm immersion lithography using high-index liquids and EUV still require a lot of research, IC manufacturers welcome double patterning as a solution to continue their research on material integration for the 32 nm node. Although significant development is still required to make EUV production ready, EUV lithography is the preferred option for many companies for the 32 nm half pitch node due to its extendibility to 22 nm feature sizes and beyond.

"We are very pleased with the progress that we've made the last months both on immersion and EUV lithography;" said Luc Van den hove, vce president Silicon Process and Device Technology at IMEC. "We are convinced that our advanced lithography program will offer our partners early lithography solutions to continue CMOS scaling beyond 32 nm."

For more information, contact IMEC or ASML.

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