Economics tempers innovation as semiconductor industry recovers

Innovation, upturn, sustainable recovery—these terms peppered conversations, presentations, and press conferences during the week-long Semicon West 2003 conference (July 14–18; San Francisco and San Jose, CA).

Sep 1st, 2003
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Innovation, upturn, sustainable recovery—these terms peppered conversations, presentations, and press conferences during the week-long Semicon West 2003 conference (July 14–18; San Francisco and San Jose, CA). Sponsored annually by SEMI (San Jose, CA), an international industry association serving 2500 companies participating in the semiconductor and flat-panel-display equipment and materials markets, Semicon West is considered a good indicator of the health of these industries worldwide, and this year was no exception.

Like other trade shows in the past year, attendance was lighter than hoped for; registered attendance was about 55,000, down from 64,000 last year, while the number of exhibitors was once again just above 1500. But those who were there seemed intent on getting as much information as possible about the state of the industry, what the next "killer apps" might be, and which emerging technologies will have the biggest impact on their business in the near and long term.

"We have a unique opportunity in our industry to reinvent ourselves through innovation to build our own future," said Ned Barnholt, president, CEO, and chairman of Agilent Technologies (Palo Alto, CA) in his keynote presentation at the meeting. "The challenge for all of us is to understand what is the structural change in our industry and to be ready for new challenges as they come along.

Barnholt isn't alone in his belief that innovation will drive recovery in the semiconductor industry. In its annual Capital Equipment Consensus Forecast, SEMI itself is projecting 4% growth this year and 24% growth in 2004. The innovation is tempered by economics, however.

A year ago, the semiconductor industry was still following an orderly plan for optical lithography from 248 nm, to 193 nm, to 157 nm and extreme ultraviolet (EUV), and whereas wavelength nodes had historically been placed six years apart the transition to 157 nm had been optimistically accelerated to four years, according to Robert Sell, manager of marketing and strategy development for semiconductor materials at Corning (Corning, NY).

But this year, 157 nm is back to the six-year mark in 2007, and EUV projections are back to six years beyond that, at 2013. In addition, the industry is no longer on one roadmap, with Intel (Santa Clara, CA), on the one hand leading an effort to skip 157 nm entirely, and others such as Nikon (Tokyo, Japan) and ASML (Veldhoven, The Netherlands) on the other hand developing immersion lithography.


IMEC Industrial Affiliation Programs are targeting new process steps and modules for development of 193 and 157 nm, as well as ultraclean process technology (left). Activities also include development of advanced CMOS processes for item such as this 90-nm CMOS silicon wafer (right).
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That said, no one is putting all their eggs into any one basket, according to Patrick Martin, director of research at mask maker Photronics (Allen, TX), which has established cross-functional technology teams to meet demands for the 90-nm node starting next year and the 65-nm in 2005. So despite leading an effort to skip 157 nm, Intel is still represented in the IMEC (Leuven, Belgium) Industrial Affiliation Program for investigating advanced lithography, which is currently working with a full-field 157-nm lithography system supplied by ASML (see figure).

Barriers remain

The fudging of timelines and broadening of technology focus are no doubt largely due to the extended economic downturn, which has everyone taking a more sober look at the daunting technology barriers that need to be overcome as well as the massive economic investments that will be required to do so.

For instance, because of very expensive optical technology barriers at 157 nm as well as for EUV, Burn Lin, senior director of the micropatterning technology division at Taiwan Semiconductor Manufacturing (Hsin-Chu, Taiwan, China) argues that successive improvements in immersion lithography along with increasingly lithography-friendly chip designs may well bridge 193-nm lithography tools all of the way down to the 32-nm node. Lin, who also taught the SPIE short course "Lithography for Non-lithographers" this year, said that immersion tool prototypes are likely to be available in 2004 with production tools available in the 2005–2006 time frame.

Christophe Pierrat, formerly with Numerical Technologies (Tokyo, Japan) and now with of Fortis Systems, who taught this year's SPIE short courses "The Limits of Optical Lithography and Advanced Lithography," was less sanguine about the barriers yet to be overcome for immersion lithography. He listed 193-nm lithography for lines and spaces assisted by resolution enhancement techniques (such as attenuated phase shifting masks, and off-axis illumination) down to the 65-nm node at the top of his potential solutions for printing lines and spaces. But he stuck with the International Technology Roadmap for Semiconductors projection for printing contacts at the 65-nm node using 157-nm lithography.

"SEMI members see the long-awaited recovery materializing," said Stanley Myers, president and CEO of SEMI commenting on member survey data released at the meeting. "Following a two-year downturn in which the worldwide market declined about 60% from the historic levels of 2000, survey participants believe that the equipment market will begin a gradual broad-based recovery this year. Furthermore, they see double-digit growth in each of the next two years as chip makers install 300-mm facilities and gear up for advanced technologies."

Nevertheless the optimists remain cautious. Even though development work for EUV is already generating orders at Corning for materials, "we'd still prefer to figure out what we're going to do in the next three years before worrying about eight years from now," Sell said.

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