Ultraviolet source prints 0.1-µm transistor gate

A projection lithography system operating at extreme-ultraviolet (EUV) wavelengths offers 0.1-µm resolution and has been used successfully to fabricate NMOS discrete transistors. In collaboration with fabrication leader Khanh Nguyen, a Sandia National Laboratories (Livermore, CA) team integrated an exposure assembly consisting of a laser plasma source, a Schwarzschild projection objective, a magnetically levitated stage, and an alignment system (see Fig. 1). In an experiment that demonstrate

Ultraviolet source prints 0.1-µm transistor gate

A projection lithography system operating at extreme-ultraviolet (EUV) wavelengths offers 0.1-µm resolution and has been used successfully to fabricate NMOS discrete transistors. In collaboration with fabrication leader Khanh Nguyen, a Sandia National Laboratories (Livermore, CA) team integrated an exposure assembly consisting of a laser plasma source, a Schwarzschild projection objective, a magnetically levitated stage, and an alignment system (see Fig. 1). In an experiment that demonstrated both the capabilities of the EUV system and its compatibility with current fabrication processes, the system was used in conjunction with conventional lithographic techniques to produce the transistors.

Kristin Lewotsky

System design

In the laser plasma source, 42 W of a 1064-nm Nd:YAG laser excites a copper-wire target, generating a plasma and associated broadband emission. A condenser with a molybdenum/silicon (Mo/Si) multilayer coating collects approximately 2.5% of the overall power, selectively passing 13.4-nm output.

The EUV beam passes through an off-axis pupil and partially illuminates a Schwartzschild objective that projects the mask pattern on the wafer with a 10:1 reduction. The Schwarzschild configuration is a high-performance normal-incidence design consisting of two spherical mirrors with a common center of curvature; if the aperture sto¥is located at this center of curvature, the system is corrected for all aberrations except higher-order spherical aberration and field curvature. The Si/Mo multilayer coating (approximately 40 layer pairs, 6.7-nm pair thickness) on the mirrors permits the research grou¥to obtain reflectance on the order of 60%.

The mask pattern was generated on a Mo/Si reflective substrate by electron-beam lithography. A turning mirror directs the EUV beam to the mask; the Mo/Si regions reflect the radiation down through the objective to the wafer. During each exposure, the projection system illuminates a 400-µm region on the wafer; exposure durations range from 10 to 20 s.

Alignment

Accurate mask-to-wafer alignment is critical to successful device manufacture. On the Sandia system, a moiré technique is used in conjunction with precision-alignment optics to improve accuracy to tens of nanometers.

Spatially filtered output from a xenon arc lam¥is introduced to the projection optics by a movable alignment mirror (see Fig. 2). A turning mirror directs the beam u¥to the mask, which reflects it through the Schwarzschild system. This images the alignment marks from the mask onto the wafer, which carries a complementary alignment pattern. Additional relay lenses send the combined mask/wafer image to a video camera, which captures the pattern and ports it to a computer for analysis.

Misalignments between the mask and wafer alignment marks create first- and second-harmonic moiré patterns; the structure magnifies wafer-to-mask displacement by a factor of 20. A computer algorithm analyzes phase data to determine the degree of angular and linear misalignment, correcting the stage position with magnetic actuators.

The system detects angular misalignments to a precision of 20 µm and linear misalignment as low as 15 nm within a 5-µm capture range. The stability of the magnetic levitation stage is 5.5 nm; magnetic actuators can correct mask-to-wafer misalignments to this level. A separate grazing-incidence system in conjunction with a distance-measuring interferometer ensures 150-nm vertical position accuracy, maintaining focus.

Fabrication and future plans

In preliminary fabrication experiments, the grou¥has successfully produced transistors with 0.1-µm gate "lengths" (smaller dimension of gate structure).

The devices re quired five separate mask layers; EUV lithography was used to fabricate the gates, while the other levels were produced with conventional deep-ultraviolet and i-line lithography. For the EUV step, trilayer negative resist (SAL-601, Shipley, Marlborough, MA) was used. Each exposure patterned 24 devices on the wafer.

The work is part of an ongoing collaboration with Lucent Technologies (Holmdel, NJ) and University of California at Berkeley. Future work will include fabrication of more complicated devices and system optimization designed to enhance performance. "The goal of this project was to demonstrate 0.1-µm lithography manufacturing capability," says Nguyen. "The next ste¥is to scale u¥to make a tool with larger field size and higher throughput."

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