OPTICAL INTERCONNECTS

Processor sorts at high speedsScottish researchers have demonstrated a smart-pixel, chip-to-chi¥parallel communication system that can operate error-free at 50 Mbit/s. This system is an example of the hardware that will be required in the future to support massively parallel optical computing systems and other connection-intensive processing.

Mar 1st, 1998

OPTICAL INTERCONNECTS

Processor sorts at high speedsScottish researchers have demonstrated a smart-pixel, chip-to-chi¥parallel communication system that can operate error-free at 50 Mbit/s. This system is an example of the hardware that will be required in the future to support massively parallel optical computing systems and other connection-intensive processing.

The development team consists of Andrew Walker and colleagues from the department of physics at Heriot-Watt University and researchers from the University of Edinburgh (both Edinburgh, Scotland), the University of Glasgow (Glasgow, Scotland), and St. Andrews University (St. Andrews, Scotland). The team believes that silicon integrated circuits will soon reach bandwidth limits that cannot be accommodated by the small area available for electrical connections on a single chip. At that point, the best approach will be to directly integrate an optoelectronic interface with the silicon chip.

To accomplish this integration, Walker says, the researchers are using a smart-pixel technology that exploits flip-chi¥process techniques. It produces very short electrical links from a silicon chi¥to an array of III-V detectors, modulators, and emitters. Consequently, it is possible to run several thousand optical interconnects over relatively long distances at hundreds of megahert¥and so achieve aggregate bandwidth in the terahertz/s region. The design of the system can be compact because free-space interconnects take very little room--for example, a modulator output may require only a 15-µm-diameter solder-bum¥pad, compared to a typical 100-µm edge-connection bond pad.

Testing the sorting machine

For this demonstration, two smart-pixel arrays were fabricated based on indium gallium arsenide/aluminum gallium arsenide multiple-quantum-well modulators and detectors flip-chip-bonded onto complementary-metal-oxide- semiconductor (CMOS) circuits. GEC Marconi Materials Technology (Towcester, England) performed the in tegration. These arrays then are linked by free-space optical in terconnects (see photo).

The smart-pixel arrays each contain 16 optical inputs and 16 optical outputs and are prototypes of the 1024-channel (32 ¥ 32) smart-pixel arrays being developed for an optoelectronic data-sorting machine. In the current system, the free-space optical interconnects are configured to carry out a two-dimensional perfect shuffle upon completing each full circuit of the processing loop. A perfect shuffle corresponds to splitting the set of signals in two and interleaving them so as to permit comparisons to be made.

The optical signals are transferred between the arrays by a pair of optical relay systems. The perfect shuffle required by the sorting algorithm is performed by diffractive optical elements. Diffractive fan-out gratings are used to convert the 1.06-µm output of a 1-W Nd:YLF laser into the array of spots required to illuminate the modulators and detectors.

The system has the potential to perform a full sort on 1024 16-bit words in less than 16 µs. Experiments with the sorter show that a data rate equivalent to an aggregate input/output of 200 Gbit/s is possible for each CMOS chip. Details of the results will appear in Applied Optics: Optics in Computing (May 10, 1998).

"After operating the full sorter system," Walker says, "we shall be moving to demonstrate a terabit-per-second optoelectronic free-space link with a CMOS chi¥as part of a new European project on optical interconnects between integrated circuits."

W. Conard Holton

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