Cloud computing, social networks, and emerging 5G-enabled applications require massive computing power in , as well as significant network capacity to access and interconnect between them. This trend has accelerated the adoption of high-capacity coherent technology from long-haul into metro networks and datacenter interconnections (DCI). These shorter-reach DCI applications (around 80 to 100 km) are particularly sensitive to the cost, size, and power consumption of optical coherent transceivers.Integration, similar to what happened in the electronics industry in the last few decades, has become the key to driving down the cost and size of optical components, and has resulted in rapid advances in the field of integrated (SiPho). The SiPho Coherent Optical Sub-Assembly (COSA) is an example to show the functional integration, cost advantage, and manufacturability of silicon. It combines a coherent modulator with an integrated coherent receiver and consists of several tens of optical functionalities, all on a <1 cm2 silicon chip to achieve significantly smaller device size and lower cost.
Since the success in commercialization of the SiPho COSA, there is a further drive to build wavelength-tunable lasers using SiPho technology. Such on-chip integration of discrete optical components can lower the tunable laser cost through reducing the number of parts and through less-complex assembly. Moreover, the advanced integration or co-packaging of a SiPho tunable laser with a SiPho COSA will provide the last piece of the puzzle to build a complete SiPho solution for next-generation low-cost coherent transceivers.
Besides optical communications, compact SiPho tunable lasers with optimized performance also expand opportunities in emerging application areas such as lidar for autonomous vehicles and on-chip optical coherence tomography (OCT) for biomedical sensing.
While SiPho tunable lasers can be a cost- and space-efficient solution for coherent communications and other applications, their commercialization has not been successful due to a few limitations.
First, light emission on silicon is still not straightforward due to silicon’s indirect bandgap. One promising solution is through the integration of SiPho chips with light-emitting III-V materials via butt-coupling techniques. However, such passive alignment demands sub-micron accuracy as well as high repeatability and throughput. This is very challenging and the resultant lower laser power is not sufficient to compensate for the large loss of high-speed coherent modulators.
Second, increasing the length of the silicon cavity is a straightforward way to generate more ‘pure’ laser light (of very narrow linewidth) to carry more information in coherent communications. However, the propagation loss of a silicon waveguide is much greater than that of free-space optics and other material waveguides such as silica, making a long silicon cavity impractical.
And third, silicon has a relatively large thermo-optic coefficient. These SiPho laser cavities are therefore extremely sensitive to any thermal disturbance, for example, from ambient temperature variations or laser current changes. As a result, it is very challenging to build a SiPho tunable laser with a high frequency accuracy of <1 GHz.
SOA and integration advances
In the last few years, NeoPhotonics has been working on SiPho solutions to overcome these limitations. Our tunable laser consists of a laser gain chip directly butt-coupled to a ring-resonator-based SiPho filter chip (see Fig. 1). Here, the ring resonators are commonly used in SiPho chips as optical spectral filters. One side of the gain chip is cleaved and serves as the laser output port. This air and III-V material interface reflect 30% of the light back into the gain chip as the optical feedback. The other facet is antireflection-coated and butt-coupled to the SiPho chip.
The SiPho-based cavity is composed of two cascaded ring filters to provide lasing mode selection over a large spectral range through the Vernier effect. The light passing through two ring filters is looped back into the gain chip to provide the laser optical feedback.We have also integrated an in-house-designed, high-power semiconductor optical amplifier (SOA) to boost the laser output power. The entire assembly is then packaged in a miniaturized gold box to meet the rigors required for optical communications applications (see Fig. 2). This compact laser package, together with the ASIC control electronics, can fit into compact coherent transceivers in small form factors such as OSFP or QSFP-DD.
This simple two-stage device design (laser plus amplifier) offers some advantages. Namely, the SOA amplifier compensates for the large coupling and propagation loss of the integrated silicon waveguides. This permits long silicon cavity designs to produce “pure”-enough laser light, while still achieving high output power through SOA amplification. It also reduces optical power on the silicon chip to prevent nonlinear effects at high power levels. And finally, laser output power can be controlled through SOA current tuning. Because the SOA is outside the laser cavity, it minimizes laser cavity changes during power tuning. This separation of power control from other laser parameters simplifies the laser control method.
If we simultaneously control the two ring-resonator filters through the integrated micro-heaters, the laser wavelength can be tuned continuously (or “grid-less”) across a broad tuning range. For example, through SOA integration, the laser output power for as many as 27 wavelength channels can reach record-high values between 21.5 and 21.9 dBm across a 65 nm tuning range (see Fig. 3).This output power is the highest reported for SiPho tunable lasers. In fact, to the best of our knowledge, this is the highest output power achieved among all tunable lasers that can be used in pluggable transceivers. In addition, laser linewidth is routinely below 60 kHz, with room for improvement by optimizing the SiPho chip design. Such narrow linewidth is suitable for 400 Gbit/s and beyond high-speed .
It should be noted that the target of our developed laser prototype is to test the best performance of SiPho tunable lasers with optimized coupling between chips. For volume production, due to the distribution of chip performance and chip misalignment errors, the laser output power will be slightly lower. Also, the power consumption of a tunable laser is another critical performance parameter, especially for their use in pluggable coherent transceivers. The thermoelectric cooler (TEC) and laser designs—as well as the TEC operating temperature—all need to be optimized to improve the tradeoff between the output power, electrical power consumption, and the device reliability.
Another challenge of SiPho tunable lasers, as described earlier, is achieving accurate frequency control down to 1 GHz. Such high frequency accuracy and stability needs to be valid across the entire tuning range, over the device lifetime, against several hundred milliamps of laser current changes, and typically over an ambient temperature range of -5° to 80°C for practical communication applications. To address this issue, we have developed an on-chip sensor technology.
To verify the functionality of our integrated sensor, we changed the SOA current to tune the laser output power while monitoring the laser frequency. Due to the thermal disturbance to the laser cavity, the laser frequency drifted more than 10 GHz for a SOA current change of 200 mA. On the other hand, when we enable the sensor function, the lasing frequency can be stabilized at the original spectral location under the same testing condition, with frequency error well below the ±1 GHz target. The same sensor technology also enables, for the first time, 1 GHz frequency stability of the SiPho laser over an ambient temperature range between -5º and 80ºC.
SiPho for products
The marriage of SiPho technology with tunable lasers will continue driving down the device cost due to fewer parts as well as less assembly and process steps. Major challenges remain for SiPho tunable lasers and one such challenge is to couple light in and out of waveguides of sub-micron size. To equal the performance of traditional devices using discrete optics, low-loss and high-throughput chip coupling is required. We need innovations in SiPho chip layout designs, optimized chip-to-chip and chip-to-fiber coupler designs, and advanced automated alignment systems to achieve a commercial product in the near-term.
Yongkang Gao is a staff engineer at NeoPhotonics, San Jose, CA; e-mail: ; www.neophotonics.