Optoelectronics aims at processor bottlenecks
With an aim to make the use of board-level optical interconnection in information systems practical and economical by developing optoelectronic packaging technology compatible with standard electronic assembly processes, the High-Speed Optoelectronic Memory Systems (HOLMS) project is scheduled to conclude in September.
EDINBURGH, SCOTLAND - With an aim to make the use of board-level optical interconnection in information systems practical and economical by developing optoelectronic packaging technology compatible with standard electronic assembly processes, the High-Speed Optoelectronic Memory Systems (HOLMS) project is scheduled to conclude in September. The 36-month HOLMS project was funded at a level of slightly more than €2.5 million ($3.1 million) under the Fifth Framework Programme in optoelectronics as part of the European Union’s Research, Technological Development and Demonstration activities. Project participants included Heriot-Watt University (Edinburgh, United Kingdom), Siemens (Paderborn, Germany), Thales Communications and Supelec (France), Universität Paderborn (Paderborn, Germany), FernUniversität in Hagen (Hagen, Germany), and the Swiss Federal Institute of Technology (ETHZ; Zurich, Switzerland).
Potential commercial applications are now being explored by several of the project participants as a direct outcome of the project’s research, which focused on seamless integration of planar free-space optics, waveguides and fiber arrays into high-performance electronic systems, enabling an optoelectronic interface to solve the interconnection bottleneck between processor speed and memory bandwidth. Single-stage, high-bandwidth, low-latency optical links were used to replace the traditional high-latency multistage processor memory interconnection to reduce the main memory access latency to the range of the raw chip access time and speed-of-light signal propagation time.
“This project represents a number of enabling technologies that open up a new way of looking at computer architecture and how the whole machine operates,” says senior researcher and HOLMS project contact John Snowdon at Heriot-Watt University. “We’re seeing penetration of optics deeper into the ‘guts’ of the computer processor. Because all-silicon photonic components are expensive, our approach in general is to combine the best of both worlds using optically ‘friendly’ materials such as gallium arsenide (GaAs) for active photonic components, novel polymers for waveguiding, and silicon for switching and logic,” Snowdon added.
The board-level optical interconnection concept is based on the combination of two new optical transmission systems: planar optics that connect to commercial parallel fiber arrays and fold the optical path of a complex interconnection within a transparent substrate, and waveguides integrated in conventional PCBs for light transmission across a system board. The planar optics are combined with thin-film electronic multichip modules that contain optical and optoelectronic components, and allow optical chip input/output channels to be directly integrated on CMOS circuits .
A key milestone for project completion included a fully working microprocessor digital signal processor running an industrially motivated application using the above new technologies to provide low-latency memory.
“While this specific aim has not yet been achieved, the individual components have been fabricated and packaged to the standards specified in the HOLMS contract,” Snowdon said. “A limited version of a complete system will be demonstrated within a few months. There are plans for follow-on projects which will refine this technology and focus in particular on its deployment as an enabling technology for next-generation computer architectures.”
Snowdon also notes that a spinoff of Heriot-Watt University called Conjunct Ltd. (Livingston, Scotland) plans to launch product in the last quarter of this year which relates to the HOLMS concept of an optoelectronic interface. Details of the product are still commercially sensitive, but essentially it will provide a minimal latency, customizable fiber-to-silicon connection.