Intel CW laser on a chip just the beginning

After announcing in early January the first Raman silicon laser on a chip that produced “pulsed” radiation, Intel researchers have now demonstrated continuous-wave capability with this laser.

SANTA CLARA, CA - After announcing in early January the first Raman silicon laser on a chip that produced “pulsed” radiation (see Optoelectronics Report, January 15, 2005, p. 1), Intel researchers have now demonstrated continuous-wave (CW) capability with this laser. The CW silicon laser on a chip evolved naturally as the next step from their original pulsed device, since CW operation is necessary to the ultimate reality of all-optical computers and information-carrying networks.

“This current breakthrough silicon laser was fabricated in our fabrication facility in Jerusalem, where we have worked closely with the process engineers in Israel along with the photonics researchers here in Santa Clara,” said Mario Paniccia, director of Intel’s Photonics Technology Laboratory. “The demonstration of CW lasing in silicon is a significant milestone in demonstrating that silicon can be considered as an optical material for future photonic devices.”

As significant as the development of the CW silicon laser is to the industry, to Intel researchers it represents just one of the building blocks necessary to achieve their goal of developing a 10-Gb/s silicon photonics network. In order for the millions of board-to-board and billions of chip-to-chip copper interconnects in existing telecommunications and computer networks to be replaced by low-cost optical materials, Intel has identified six fundamental silicon building blocks: light sources, light-guiding technologies (waveguides, splitters, switches), fast modulation, light detection, low-cost assembly, and integration intelligence.

Even though the company has made excellent progress with the first building block via the CW laser breakthrough, Intel acknowledges that continued experimental work is necessary to improve overall device performance to the point where high-speed communications are possible. Particularly for the fifth building block-low-cost assembly, or what Intel calls “smart packaging”-the scientists are working on passive alignment to reduce the assembly, packaging, and testing costs of optical devices. Through passive alignment, trenches, bumps, and other features are etched into the silicon surface to enable high-speed, high-precision placement of devices.

“We expect to see products using silicon photonics components in the latter half of the decade,” says Intel’s R&D media relations representative Kevin Teixeira. “Having said that, we are also pursuing a hybrid approach whereby if a silicon component is not ready yet, we would integrate an off-the-shelf component if necessary.”

Because Intel’s core business is personal computers and servers, the most likely first application for silicon photonics will be in optical backplanes. And as the cost of silicon photonic devices declines further, Intel expects to see them used for interconnects in and around personal computers.

-Gail Overton

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