Moore’s law envelops SEMICON West
SAN FRANCISCO, CA—Moore’s law and its relentless dictation of finer and finer feature sizes on integrated circuits (in concert with expected pricing drops), was ever-present on the minds of attendees, presenters, and exhibitors at this year’s SEMICON West 2008, held July 15–17 in San Francisco, CA.
SAN FRANCISCO, CA—Moore’s law and its relentless dictation of finer and finer feature sizes on integrated circuits (in concert with expected pricing drops), was ever-present on the minds of attendees, presenters, and exhibitors at this year’s SEMICON West 2008, held July 15–17 in San Francisco, CA. It seems that everyone is nervous trying to figure out how to improve chip performance and minimize size and power consumption, while simultaneously figuring out how to deal with falling prices. The fervor was well illustrated in the long lines for customers waiting to buy the new iPhone G3 at the Apple store in San Francisco, ironically filing past advertisements that shouted, “Twice the Performance; Half the Price.”
As a first-time attendee to this conference, I underestimated the need for comfortable shoes. This year’s event filled the North, South, and West Halls of Moscone Center (with events in the Novellus Theatre and Marriott and InterContinental Hotels) and hosted well over 45,000 registered attendees and 1151 exhibitors. The North and West Halls hosted their own TechXPOTS (“tech spots”)—technology-focused “shows-within-a-show” on such topics as Challenges in Device Scaling, Emerging Markets, and Test, Assembly & Packaging.
Intersolar North America’s co-location with SEMICON West (for the first time) was a strategic move on the part of SEMICON West conference organizer SEMI (San Jose, CA), which calls itself the “only truly global representative of the semiconductor, display, MEMS and related industries” market, to expand its technology focus to include the dynamic photovoltaic (PV) market sector. “About 20% of SEMI’s 2,000 member companies are already active in the photovoltaic sector,” said Bettina Weiss, senior director, PV, SEMI North America. “SEMI’s existing core competencies in standards, industry research and statistics, shows/conference, public policy, and other areas have been extended to include PV, and unique approaches for new products, services and initiatives for unique PV manufacturing challenges are currently being developed.”
Weiss added that SEMI and Intersolar have entered into partnership agreements for Intersolar Europe in Munich in May 2009 as well as the continuation of the Intersolar North America show to be co-located with SEMICON West again in 2009.
Moore’s law in a down market
Moore’s law—loosely cited as the exponential increase in the number of transistors that need to be packed onto an IC in order to economically make chips (roughly, a doubling every two years)—is the driver towards smaller and smaller IC feature sizes, all while reducing the manufacturing costs for ICs. Exacerbating the pressure is the fact that market analysis and forecasting firms call for a downturn in the semiconductor equipment market in 2008.
In Monday’s SEMI Market Symposium, co-presented by SEMI and research and advisory firm Gartner Dataquest (Stamford, CT), 2008 was being called “a year of sadness” by Dean Freeman, research VP at Gartner Dataquest. Freeman said that the downturn in the semiconductor industry was so far the fourth worst since data collection began in 1982 by Gartner, citing the biggest challenges as shrinking margins, fewer customers due to industry consolidation, and the fact that easy scaling in the semiconductor industry (in terms of both materials and equipment) had ended.
Market Symposium keynote speaker Jim Clifford, senior VP and GM of operations at Qualcomm CDMA Technologies (San Diego, CA), had a somewhat more optimistic view of the future of the semiconductor industry. In his keynote entitled “A Changing Model for a Changing Landscape,” Clifford described how consumer handsets (portable, mobile devices) are more popular than desk-top computers and that there are more cell phones with cameras in use today than there are digital still cameras, indicating that consumers are thirsty for gadgets with lots of semiconductor chips in them. He points to emerging markets such as China and India, bringing the forecasted total for handsets to 1.6 billion by 2012.
Technology and business innovation
But for all this demand in sheer volume and phone performance, customers are also demanding price decreases, driving overall margins lower. Klaus Rinnen, managing VP at Gartner Dataquest, predicted in his SEMI Market Symposium presentation that the compound annual growth rate (CAGR) between 2008 and 2012 will slow to approximately 4.9%, compared to the approximate 17% in the four years prior to 2008. Despite progress in three-dimensional (3-D) stacked wafer technologies to add increasing performance and chip density, power consumption and stagnant materials cost with this methodology is still an issue. Rinnen takes a longer-term look at semiconductor manufacturing and points to the 2018 time horizon when today’s classic materials and processes will be disrupted by DNA logic and other polymers, molecular transistors, and quantum computing—technology innovations that manufacturers need to start exploring today if they want to maintain viability tomorrow.
Senior director of industry research and statistics at SEMI, Dan Tracy arrived at similar forecasting numbers to Gartner Dataquest, despite “independent” analysis. Tracy and SEMI forecast an approximate 20% decline in the semiconductor capital equipment market for 2008.
The answer for many manufacturers wanting to bypass the higher-volume/smaller-margin dilemma in the semiconductor industry was best highlighted by Yukio Sakamoto, president and CEO of Elpida Memory (Tokyo, Japan), a manufacturer of dynamic random access memory (DRAM) silicon chips. In his Tuesday morning Keynote presentation, Sakamoto described how his company was reducing the salary of its executive staff, but more importantly, moving from a high-volume me-too manufacturer to a high-growth niche manufacturer, already moving from 70 nm down to 50 nm feature sizes to aggressively enter the “emerging” growth markets for higher-end consumer devices that demand better performance and lower energy consumption. Sakamoto explained how companies must move from being device manufacturers to partnering with other companies to be “system solution” providers—a concept much touted during the telecom boom. Unfortunately, the boom went bust anyway, shedding doubt on the viability of Sakamoto’s proposal.
Appropriately entitled “Semiconductor Technology: a Convergence of Technology and Business Models,” the keynote presentation from Bernie Meyerson, VP for strategic alliances and CTO of IBM Systems and Technology Group (Armonk, NY), best summarized the business/technology convergence so widely discussed at SEMICON West 2008. Meyerson has broadly analyzed the R&D investment needed to faithfully execute Moore’s law, and reached the conclusion that investing 12.2% up to 2020 while reaping a 6.5% revenue stream is not a sustainable business model. He calls for globalization of semiconductor R&D to cushion these enormous development costs, pointing to the demand for lower energy consumption devices in a rising-fuel-prices economy, the need for computational lithography as even EUV won’t meet the roadmap past 2020, and even discussed the need for integrated optics to play a larger role in improving semiconductor manufacturing and architecture development with technologies such as light-emitting single-carbon-nanotube transistors playing a role in next-generation devices.
Imprint versus EUV lithography
While the keynote and market presentations at SEMICON West focused mostly on the “health” of the semiconductor industry, technologists are clearly focused on the nitty gritty of building better chips. The move towards smaller and smaller integrated-circuit (IC) feature sizes from the current 90 nm or more down to the desired 22 nm level is driving the technology of lithography to new and competitive levels. On the one hand, there is the extreme ultraviolet (EUV) approach—an extension of existing lithography technology that depends on an ever-smaller wavelength of light (13.5 nm in this case to produce 22 nm features) and currently in the R&D stage at several academic institutions as well as at Cymer (San Diego, CA) and Gigaphoton (Mountain View, CA). But on the other hand, there is the nanoimprint lithography (NIL) option from suppliers such as Molecular Imprints (Austin, TX)—already capable of 22 nm features, but still challenged in terms of speed and defect levels.
Although the technology roadmaps for both NIL and EUV can be debated (see www.laserfocusworld.com/articles/298394), results from a recent survey of semiconductor industry insiders by Wright Williams & Kelly (WWK; Pleasanton, CA), a cost & productivity management software and consulting services company, showed that 50% or more of the respondents expect to see imprint lithography in production between 2010 and 2012 (as well as 193 nm high-index immersion lithography), whereas survey respondents did not expect to see EUV lithography in production until 2014 or beyond. The client base of WWK includes nearly all of the top 20 semiconductor manufacturers and equipment and materials suppliers as well as leaders in nanotechnology, micro-electro-mechanical systems (MEMS), flat-panel displays (FPD), and photovoltaics (PV).
“With over 200 new products introduced at this year’s SEMICON West, to be singled out by this diverse panel of judges is an enormous achievement,” said Tom Morrow, VP of global expositions at SEMI, referring to the announcement that Jenoptik (Jena, Germany) and Alchimer (Massy, France) received the 2008 SEMI Best of West award. Jenoptik won for its “JENOPTIK-VOTAN G Semi,” a wafer dicing system that utilizes thermal laser separation (TLS), an alternative to established mechanical dicing saws and other laser dicing technologies to deliver a precise cutting edge and well suited to applications with special demands on edge quality. Alchimer won for its GViaCoat for the electrografting of copper seed layers used for the metallization of through silicon vias. The technology uses a wet electrochemical process based on specific organic precursors to enable the initiation and growth of thin films on conducting and semiconducting surfaces.
Semicon West 2009 will once again be held in San Francisco, CA from July 14–16, so bring your walking shoes! —Gail Overton