Europe tackles tough EUV-lithography issues
EUROPEAN UNION--As those who are clued in to the semiconductor industry know, the smallest feature size found on the current generation of leading-edge computer chips is 45 nm, and the next generation (which manufacturers are working on now) will have a minimum feature size of 32 nm.
EUROPEAN UNION--As those who are clued in to the semiconductor industry know, the smallest feature size found on the current generation of leading-edge computer chips is 45 nm, and the next generation (which manufacturers are working on now) will have a minimum feature size of 32 nm. Subsequent generations are slated to jump to 22 nm, then to 16 nm.
At the moment, deep-UV (DUV) lithography, which operates at 193 nm using water immersion to boost the imaging lens numerical aperture to above 1, and which relies on fancy exposure tricks and--most of all--ultraprecise optical systems and photomasks, is adequate for fabricating leading-edge chips. But soon DUV will have run its course, and the industry will have to switch to extreme-UV (EUV) lithography, which uses light at 13.5 nm.
The most-often-mentioned challenges in EUV technology are the light source and the imaging optics; these are on their way to practicality, in the form of Cymer's (San Diego, CA) laser-produced-plasma source and ASML's (Veldhoven, The Netherlands) all-mirror optics with a resolution of 10 nm and potentially smaller. But two of the toughest challenges lie in alignment and in photomask quality, which are extremely important for the last iterations of DUV lithography as well.
One of the most important measurements is the alignment between the numerous layers that make up a semiconductor chip. The maximum error the manufacturer is prepared to accept is known as the overlay-control budget. To help develop EUV alignment to a production-worthy level, an EU-funded project, SOCOT (Scatterometry Overlay COntrol Technology), was set up, bringing together a vendor of metrology (measuring) tools, a software developer with experience in metrology, a chip manufacturer, and an R&D center.
Project coordinator Daniel Kandel says the EU project was necessary "because there was a significant risk that, at 32 nm, no existing technology could measure the alignment between layers with sufficient precision and accuracy." He points out that a 32-nm-wide line is only the width of 59 silicon atoms. "The measurement accuracy is typically one-tenth of the error that can be tolerated, so in this case, the metrology has to be accurate to 0.3 nm or 3 angstroms," says Kandel.
The SOCOT researchers have taken a whole new metrology approach--that of scatterometry. Current technology involves looking at images of patterns on adjoining layers with a microscope, but this will not work when trying to spot 0.3 nm misalignments. The researchers decided to experiment with scatterometry, a technique already in use for other types of measurements in chip-manufacturing facilities.
"Using the measuring tool we have developed, you illuminate the wafer with light of a variety of wavelengths and then measure the scattered light," says Kandel. "We have developed sophisticated software programs or algorithms which allow us to calculate the level of misalignment from the light signatures." In SOCOT's R&D environment, a misalignment measure of 3 angstroms accuracy was achieved.
Towards production-worthy reticles
Since the 2009 International EUVL (EUV Lithography) symposium held Oct. 18 to 23 in Prague, Czech Republic, the creation of a photomask (also called a reticle) of high-enough quality has become the number-one critical issue in preparing EUVL for high-volume manufacturing.
At IMEC (Leuven, Belgium) researchers are using a combination of three inspection techniques--blank inspection, patterned-mask inspection, and wafer inspection--to evaluate the "defectivity" level of state-of-the-art reticles for EUVL. IMEC uses the combined techniques, followed by wafer review, as the most suitable method to qualify defect densities of EUV masks.
A blank is the starting material for the fabrication of the mask. Mask defects can be due to the pattern or due to the blank. Wafer-inspection detection is confined to detecting repeating defects among multiple exposures, as these represent mask defects. The correlation of the defect maps obtained from each of the three types of inspections is crucial, because at present, none of the available inspection methods is sensitive enough on its own to find all defects.
By using this combined inspection, the defectivity level of state-of-the-art EUV reticles can be investigated. In addition, possible gaps in the available EUV mask-inspection infrastructure can be identified; these will need to be closed before EUV is ready for the production of integrated circuits.
The record defect density of a present "champion" reticle is 0.53 defects per square centimeter. Although this low defect density is very encouraging, it is still more than ten times higher than the industry's target of a defect density below 0.04 defects per square centimeter.