The A*STAR Institute of Microelectronics (IME; Singapore) has launched two consortia for advanced packaging: the Silicon Photonics Packaging consortium (Phase II) and the MEMS Wafer Level Chip Scale Packaging (WLCSP) consortium. Each will develop novel solutions in the heterogeneous integration of MEMS and silicon photonics devices, which will improve overall performance and reduce production costs.
In Phase I of the Silicon Photonics Packaging Consortium, IME and its industry partners had developed new capabilities in device library and associated tool boxes to enable the integration of low profile lateral fiber assembly, laser diode, and photonics devices. By employing a laser welding technique, the consortium demonstrated a fiber-chip-fiber loss of less than 8 dB with less than 1.5 dB excess packaging loss.
In Phase II, the Consortium will further develop low loss silicon coupling modules, and provide a series of packaging solutions for laser diode integration. It will also focus on developing accurate thermal models, as well as improve overall module thermal management, reliability, and RF performance to meet very high data bandwidth demand. All these developments will lead to a more integrated packaging solution that promises better assembly margins and lower module costs. Members of the consortium include: Accelink Technologies, Corning, Fujikura, Fraunhofer Heinrich Hertz Institute, and NTT.
The IME MEMS WLCSP Consortium has also been established to develop a cost-effective integration packaging platform for capped MEMS and CMOS devices. This platform could be used for any MEMS devices with cavity-capping such as timing devices, inertial sensors, and RF MEMS packaging.
“These capabilities will enable our industry partners to capture new growth opportunities in the Internet of Things (IoT) space and accelerate market adoption of cost-effective technologies,” said Prof. Dim-Lee Kwong, Executive Director of IME.
Source: A*Star IME