The global semiconductor chip shortage has led to significant frustration as organizations across many industries have resorted to plan B. However, it has also prompted significant investment in research and development efforts necessary to find new solutions.
Case in point – IBM and Samsung Electronics are jointly announcing a breakthrough that defies conventional semiconductor design and aims to reduce the energy usage of chips by 85 percent or double performance compared to scaled finFET transistors.
Developed by a joint team of researchers at the Albany Nanotech Complex, IBM and Samsung's new VTFET design prototype successfully implements transistors built vertically on the surface of a chip. Because transistors have, until now, been built horizontally to lie flat upon the surface of a semiconductor, this allows an exponential number of transistors to exist on a chip and removes density and energy efficiency constraints.
“We see high bandwidth communication between chips as advanced interconnect becoming more important in the years to come. Lasers, photonics and optics will have a critical role to play in these innovations,” Huiming Bu - Vice President, Hybrid Cloud Technology Research & Albany Operation, IBM Research tells Laser Focus World. “These adjacent technologies have continued to play an increasing role in system integration, and it is anticipated they would bring complementary values in parallel along with transistor architecture innovations well into the future.”
The VTFET process addresses many barriers to performance and limitations to extend Moore’s Law as chip designers attempt to pack more transistors into a fixed space. It also influences the contact points for the transistors, allowing for greater current flow with less wasted energy. Overall, the new design aims to deliver a twotimesimprovement in performance or an 85 percent reduction in energy use as compared to scaled finFET alternatives.
“We believe the areas of EDA, inline metrology and process control (controlling physical parameters along the vertical Z direction in mass production) are areas of rich opportunities for VTFET adoption in the industry,” says Bu. “We are introducing this new device architecture at IEDM this year and hence not associating it to any specific technology node yet. Our intent is to introduce the VTFET architecture with its many advantages and unique features. The actual node adoption is aimed to be after Nanosheet Technology.”
