MICHAEL J. LANGE, PETER DIXON, MARSHALL COHEN, and JIAN ZHAO
Planar p-n junction formation has historically been one of the most difficult fabrication steps for indium phosphide/indium gallium arsenide phosphide (InP/InGaAsP) devices such as detectors. Unless special precautions are taken, the material system tends to decompose when exposed to temperatures above 350°C, and most diffusion processes require temperatures exceeding 500°C to form a planar p-n junction.
Traditionally, the largest demand for InP-based optoelectronic components has been in the area of small-footprint diode lasers and photodiodes. While thousands of these chips can be fabricated from a single 50-mm-diameter InP wafer, there has not been a lot of pressure on the industry to increase wafer size to 100-mm diameters, even with increasing demand for the components. This may soon change, though, because of the recent influx of devices such as near-infrared (IR) cameras, dense-wavelength-division-multiplexing (DWDM) monitors, large-area power meters, and VCSEL arrays, which integrate large numbers of components and have substantially larger footprints. Demand for these new devices is driving the need to fabricate larger wafers in greater volume, a move that also has made improving p-n junction formation in InP a top priority for many detector manufacturers.
While ion implantation is the most common technique for the silicon and GaAs material systems, it is not very useful for InP-based devices that require deep junctions and diodes with very-low leakage current, examples of which include InGaAs/InP near-IR staring detectors and high-speed detectors. High-quality reliable devices with low leakage current typically require junction depths greater than 1 µm. The energy necessary to implant p-type dopants to these depths generally introduces irreparable damage to the crystal that degrades device performance.
The most common low-cost technique for planar junction formation in InP/InGaAs detector manufacturing is the sealed-ampoule diffusion technique. This process seals patterned InP wafers under vacuum inside a quartz ampoule, along with some dopant source and a decomposition suppressant. The junction pattern is typically etched through a silicon-dioxide or silicon-nitride mask. The dopant source for p-n junction formation is usually solid-phase zinc, although cadmium also has been used. Zinc and cadmium are p-type dopants, so the InP-based semiconductor material must be n-type for a diode junction to be formed. This type of diffusion is not realistic for InP-based material systems because the temperature requirement far exceeds the decomposition temperature even when a Group V decomposition suppressant is used.
Diffusion takes place within a furnace typically operating at typical temperatures between 450°C and 600°C, with the doping-composition profile depending on temperature and the crystal properties of the wafers. The dopant source and Group V material sublime until a steady-state partial pressure is achieved for each species. At steady state, the vapor-phase composition of the dopant is constant for any given temperature, and the diffusion depth can be modeled by the lumped parameter equation
Depth = D(t - t0)1/2
where D is a constant dependent on temperature, t is the diffusion time and t0 is the time for the system to reach equilibrium.
At first glance, this process appears difficult to control and implement in a manufacturing environment; however, it works surprisingly well for many applications. One problem is that it does not scale well to large-diameter (100-mm) wafers or automated processes required for higher-throughput manufacturing.
The reactor chamber, which often uses a converted epitaxial-growth reactor, is another common technique for zinc diffusion. Wafers are brought to the diffusion temperature within a phosphine-rich environment to suppress decomposition of the exposed InP. Adding a gas source such as dimethyl zinc to the chamber then causes diffusion. The reactor chamber, which works well if there is proper control of temperature and gas flows, can handle large wafers in large volume. The problem with this method revolves around the expense of purchasing and maintaining the equipment and the caution required when handling phosphine gas.
Spin-on glass diffusion
A relatively new technique for junction formation, at least within the InP/InGaAs material system, is spin-on glass diffusion, a process that has been available for many years for silicon and is still used in some low-cost silicon processes. These days, though, ion implantation and carrier-gas diffusion dominate most silicon production, and spin-on glass doping for silicon has mostly been relegated to undergraduate electronics laboratories because of its relative simplicity and low cost. These same features, though, make the process attractive for fabrication of InP-based diodes.
As in the more common techniques, the process involves the patterning of a dielectric layer to expose the InP surface where diffusion is to occur. The InP is slightly etched to a depth as shallow as 10 nm, which prepares the surface and also delineates the pattern to allow for subsequent mask alignment. The zinc phosphide glass dopant is then applied to the wafer surface through conventional spin-coating, a process similar to photoresist dispensing.
During processing, the spin speed should be set as high as possible, while still ensuring that the amount of doping on the surface can be considered infinite. The glass thickness that can be considered infinite will depend on the desired junction depth. The deeper the junction, the thicker the glass doping film must be. The glass film must not be thicker than necessary, though; otherwise, cracking could become a problem during the drive-in sequence.
As shown by the following equation, diffusion is by a fixed initial surface concentration instead of a constant surface concentration:
C(x,t) = Cserfc[x/2(Dt)1/2]
Here, C(x,t) is the concentration of zinc as a function of depth and diffusion time, and Cs is the initial "infinite" surface concentration.
In the process, after the doping glass is applied, the solvents are baked off and the surface is mildly oxidized by oxygen-reactive ion etching. The wafer surface is then capped with a dielectric film before diffusion drive-in. These diffusions have been accomplished in both a furnace tube and by rapid thermal annealing (RTA). While the first annealing process poses less of a risk for cracking the glass film, the RTA method is preferable for automated high-throughput fabrication.
In recent experiments, scientists have used RTA to form junctions greater than 1-µm deep in less than 4 min at 600°C, with the key to doing so being to slow down the ramp rate to prevent film cracking. The glass film, dielectric diffusion mask, and capping layer are all removed in dilute hydrofluoric acid; and a fresh passivation dielectric film is applied before standard fabrication resumes.
Continued process improvements
Formation of p-n junction by spin-on glass diffusion has been successfully demonstrated for the InP/InGaAs material system. This method is low-cost, scalable to large wafers, and compatible with automated wafer-handling and process control. It also does not introduce highly toxic materials or require additional capital expenditure. Spin dispensers, reactive ion etchers, and RTAs are already standard equipment in most InP fabrication facilities.
Recent experimental results also have addressed one of the remaining issues of concern regarding zinc diffusion in InP. This issue pertains to variation in the "active" zinc concentration across a large wafer or from wafer to wafer, a problem likely caused by variation in the phosphorus vacancy concentration in the epitaxially grown material. SIMS data shows that the chemical composition of zinc is relatively uniform across a wafer or from wafer to wafer, while Polaron sometimes shows a large variation in the active concentration that can be some 50 times lower than that measured by SIMS. The result is that, in many cases, most of the zinc sits at interstitial sites within the InP lattice and not at active substitutional sites. Some of the interstitial zinc is neutral, and some actually acts as an ionized donor that compensates the acceptor nature of the active zinc dopants. Also, the interstitial zinc (both neutral and ionized) is highly mobile.
A spin-on glass method developed at Sensors Unlimited and Rutgers University increases the active concentration of zinc, while virtually eliminating the potentially damaging interstitial zinc. This method, which also improves the spatial uniformity of the active zinc concentration in InP, is quite simple. After diffusion by any method, the process applies a fresh dielectric layer to the InP wafer. The wafer is then annealed in an RTA at a temperature above the initial diffusion temperature for less than 30 s.
Polaron and SIMS measurements confirm that this procedure increases the active zinc concentration significantly, while driving the remaining mobile interstitial-zinc atoms to the InP surface. These results could have a significant impact on future device and fabrication designs developed using the spin-on glass doping technology.
ACKNOWLEDGMENT
This work was partially supported by the National Institute of Standards and Technology through an advanced technology program (contract no. 70NANB8H4015).
Michael J. Lange is the director of processing research, Peter Dixon is a processing department manager, and Marshall Cohen is the executive VP at Sensors Unlimited, Inc., 3490 US Rte 1, Princeton, NJ 08540; e-mail: [email protected]. Jian Zhao is a professor of electrical engineering at Rutgers, the State University of New Jersey, Newark, NJ 07102.