CMOS SENSORS: Optical confinement enables CMOS-sensor scaling
As the demand for higher-resolution complementary metal-oxide semiconductor (CMOS) image sensors continues to increase for cell-phone and digital-camera applications, shrinking CMOS pixel sizes present new challenges for sensor designers.
As the demand for higher-resolution complementary metal-oxide semiconductor (CMOS) image sensors continues to increase for cell-phone and digital-camera applications, shrinking CMOS pixel sizes present new challenges for sensor designers. As pixel dimensions approach the wavelength of visible light, diffraction can cause increased crosstalk between pixels; also, smaller pixel sizes make photon collection more difficult. For continued CMOS sensor scaling to smaller and smaller pixel sizes, a team of researchers led by Peter Catrysse, an engineering research associate in the Department of Electrical Engineering at Stanford University (Stanford, CA), has studied a variety of methods that can channel light from a microlens array down to a CMOS photodiode to determine which methods maximize optical efficiency.1
A CMOS image sensor is a three-dimensional stack consisting of microlens and color-filter arrays and several dielectric layers. Each microlens focuses light from the image onto a silicon oxide layer, followed by a color filter, then through a silicon nitride passivation layer and into the thickest oxide layer that provides support and isolation for the metal interconnects, and finally to the silicon substrate where the photodiode is formed and light is absorbed.
Light-guiding inside pixels can be accomplished through two mechanisms: total internal reflection (TIR), or reflection at a metal-dielectric interface. To achieve optimal light confinement, different CMOS sensor light-guide designs can be implemented (see figure). The first uses air gaps within the thick oxide layer that act as a low-index cladding to channel light to the photodiode. The second consists of a high-index-core design that confines light within the pixel region. And the third uses a metal-cladding light-guiding method. Essentially, the first two designs use TIR while the third uses reflection at a metal-dielectric interface to optimize light-guiding efficiency.
Using optical efficiency and optical crosstalk as performance metrics, the researchers use a finite-difference time-domain (FDTD) modeling technique to understand the differences between the three optical-confinement methods. The simulations are for CMOS sensors with a state-of-the-art pixel pitch of 1.75 µm. Specific parameters for each of the three confinement methods are varied as part of the simulation exercise, in order to understand how to optimize the CMOS pixel light-guide designs.
For the low-index cladding confinement method, air-gap thicknesses were varied from 0.05 to 0.2 µm in 0.05 µm increments. For the high-index core confinement method, the core refractive indices were varied from 1.5 to 1.7. And in the metal-cladding confinement method, two different metals were used: aluminum and tungsten. The FDTD simulations model the incident light as a continuous plane wave for incidence angles between 0° and 30°, and assume a red-colored filter since diffraction effects are most prominent at longer wavelengths.
The simulations of low-index confinement showed, in the case of the thinnest air gap, light loss due to frustrated TIR–the evanescent wave in the air gap couples over to the adjacent dielectric. With incidence angles from 0° to 10°, comparable performance was observed for 0.1, 0.15, and 0.2 µm air-gap layers; however, for incidence angles above 10°, a breakdown in confinement occured for all air-gap values. For the high-index core confinement method, the higher-index 1.7 value confines the light better due to improved TIR. And finally, for the metal-cladding method, optical efficiency is much better for aluminum over the absorptive and less-conductive tungsten material.
Both TIR methods can yield significant improvement (10%) in optical efficiency over a reference plain-pixel design, while the metal-cladding method performs best in terms of eliminating optical crosstalk. These improvements are comparable to other methods for increasing efficiency and reducing crosstalk, such as thinning the image-sensor stack. Paying careful attention to CMOS pixel design should allow scaling of CMOS image sensors to pixel sizes even smaller than 1.75 µm.
“What we have shown is that pixel light guides are, in fact, a credible alternative to stack thinning or backside illumination,” says Catrysse. “Moreover, it is likely that light guides can be used in conjunction with other approaches to keep light from spilling over in sub-1.5 µm pixels.”
- C.C. Fesenmaier et al., Optics Express 16(25) p. 20457 (Dec. 8, 2008)